1. Technical Field
The present disclosure relates to a memory device and, more specifically, to a phase change memory device and method of forming the same.
2. Discussion of the Related Art
A phase change memory device is a type of non-volatile computer memory where data is stored by changing a chalcogenide material between an amorphous state and a crystalline state. Phase change memory devices such as PRAM (phase change random access memory) have demonstrated remarkable potential to be competitive with the ubiquitous Flash memory.
The PRAM device includes an array of memory cells. Each cell includes a layer of chalcogenide phase change material with a top electrode above the chalcogenide layer and a resistive heater element below the chalcogenide layer.
FIG. 1 is a schematic of a PRAM cell structure. The PRAM cell 1000 includes a chalcogenide layer 1100 covered with a top electrode 1200. The chalcogenide layer 1100 can include an alloy of a group V or VI element such as Tellurium (Te) Selenium (Se) or Antimony (Sb). One example of a suitable chalcogenide includes Ge2Sb2Te5. A resistive heating element 1300 is below the chalcogenide layer 1100. A programming current may be applied to the top electrode 1200 by a bit line 1400. A single bit line 1400 may connect an entire column of PRAM cells 1000 within a cell matrix. The resistive heating element (heater) 1300 is below the chalcogenide layer 1100. The heater 1300 is connected to a transistor 1500 that is in turn connected to ground 1700. The transistor 1500 controls the flow of current through the PRAM cell 1000 depending on a signal received from a word line 1600. A single word line may connect an entire row of PRAM cells.
To program a cell, current is passed from the top electrode through the resistive heater. By varying the level of current, the heat of the chalcogenide layer may be changed between an amorphous state and a crystalline state. As used herein, the crystalline state may refer to a polycrystalline state where multiple crystals are formed within the same chalcogenide layer.
In its amorphous state, the chalcogenide has a relatively high resistivity. In its crystalline state, the chalcogenide has a relatively low resistivity. The difference in resistivity between the amorphous and crystalline states may vary by two or more orders of magnitude. This sharp difference in resistivity facilitates the reading of the PRAM cell by application of a read voltage Vr and measuring the resultant current. A low resultant current indicates a high resistivity corresponding to the amorphous state while a high resultant current indicates a low resistivity corresponding to the crystalline state. Each state may be assigned a particular logical value. For example, the crystalline state may correspond to a logical “0” while the amorphous state may correspond to a logical “1.”
As discussed above, phase change may be controlled by varying the level of current through the resistive heater and thus changing the temperature of the chalcogenide. FIG. 2 shows temperature curves for eliciting an amorphous state and a crystalline state for a given chalcogenide. An amorphous state is achieved by heating the chalcogenide to a temperature above the melting temperature Tm of the particular chalcogenide used and then allowing the chalcogenide to quickly cool to below the crystallization temperature Tc over a time T1. This temperature curve is shown as 2100. Because the temperature of the chalcogenide quickly cools to below a crystallization temperature Tc for the particular chalcogenide used, the chalcogenide is not given an opportunity to crystallize and thus remains in an amorphous state. A crystalline state is elicited by heating the chalcogenide to a temperature above the crystallization temperature Tc but below the melting temperature Tm. The temperature remains above the crystallization temperature Tc over a slow cooling time T2. This temperature curve is shown as 2200. Because the temperature of the chalcogenide remains above the crystallization temperature but below the melting temperature for a sustained period of time, the chalcogenide is allowed to crystallize.
A single heater element may be used to produce each of the desired temperature curves. The heater element generates the desired heat by resisting the flow of current and converting electrical energy into heat. Accordingly, higher temperatures may be achieved by increased current. Similarly, a short time T1 is achieved by using a short pulse while a slow cooling time is achieved by using a long pulse.
FIGS. 3 to 6 show a fabrication process for manufacturing a conventional PRAM device. As seen in FIG. 3, an isolation layer 5 is formed on a semiconductor substrate 1 using an isolation process. The isolation layer 5 includes an oxide that functions as a mask during a doping process. The doping process defines an active region within the substrate 1 not covered by the isolation layer 5. Gate structures 25 are formed on the active region of the substrate 1. Each gate structure 25 includes a gale oxide layer pattern 10, a gate electrode 15 and a gate spacer 20. The gate electrode 15 is formed using a doped polysilicon or a metal. The gate spacer 20 is formed using silicon nitrite. A source region 30 and a drain region 35 are formed at portions of the active region adjacent to the gate structure 25 by an ion implantation process. A first insulating interlayer 40 is formed on the substrate 1 having the source 30 and the drain 35 regions to cover the gate structures 25. The first insulating interlayer 40 is generally formed using a silicon oxide.
As seen in FIG. 4, contact holes (not shown) are formed through the first insulating interlayer 40 by partially etching the first insulating interlayer 40. The contact holes expose the source 30 and drain 35 regions, respectively. Each of the contact holes has an upper portion and a lower portion, with the upper portion being wider than the lower portion.
A conductive layer (not shown) is formed on the source region 30, drain region 35 and the insulating interlayer 40. The conductive layer fills the contact holes. The conductive layer includes a doped poly silicon or a metal. The conductive layer is then removed exposing the first insulating interlayer 40. A first contact 45 and a second contact 50 may then be formed in the contact holes. The first contact 45 is formed on the source region 30 and the second contact 50 is formed on the drain region 35. A second insulating interlayer 55 is formed on the first insulating layer 40 and covers the first contact 45 and the second contact 50. The second insulating interlayer 55 is partially etched and an opening 60 is formed that exposes the first contact 45. The second insulating interlayer 55 is generally formed using silicon oxide.
As seen in FIG. 5, an insulation layer (not shown) is formed at the bottom of the opening 60 (FIG. 4), a sidewall of the opening 60 and on the second insulating interlayer 55. The insulation layer is etched and a spacer 70 is formed on the sidewall of the opening 60. The spacer 70 is formed using silicon nitride. A lower electrode layer is formed on the exposed first contact 45 and the second insulating interlayer 55. The lower electrode layer is then removed by a chemical-mechanical planarization (CMP) process until the second insulating interlayer 55 is exposed. A lower electrode 65 is thereby formed in the opening 60. The lower electrode 65 is formed using a metal or metal nitride. A phase-change material layer 75 and an upper electrode layer 80 are successively formed on the lower electrode 65 and the second insulating interlayer 55. The phase-change material layer 75 is formed using chalcogenide. The upper electrode layer 80 is formed using a metal or metal nitride.
As seen in FIG. 6, the upper electrode layer 80 and the phase-change material layer 75 are patterned and a phase-change material layer pattern 85 and an upper electrode 90 are formed on the lower electrode 65 and the second insulating interlayer 55. A third insulating interlayer 95 is formed on the second insulating interlayer 55 to cover the upper electrode 90. The third insulating interlayer 95 is formed using silicon oxide.
As PRAM devices must have a high density of memory cells to be commercially viable, the total energy dissipated by the set of resistive heater elements can be substantial. In addition to relatively high power consumption, the substantial level of heat generated may be detrimental to the PRAM device and its surrounding components. Moreover, the relatively high power consumption and the substantial level of generated beat can impose limiting design constraints on PRAM devices.